Logic (RTL / Physical) Synthesis
Description
Logic Synthesis
Logic synthesis is a process by which an abstract form of desired circuit behavior, typically at register transfer level (RTL), is turned into a design implementation in terms of logic gates, typically by a computer programme called a synthesis tool. Common examples of this process include synthesis of HDLs, including VHDL and Verilog.
High-level synthesis or Behavioral synthesis
Today, high-level synthesis, also known as ESL synthesis and behavioral synthesis, essentially refers to circuit synthesis from high level Languages like ANSI C/C++ or SystemC etc. to RTL Level, whereas Logic Synthesis refers to synthesis from structural or functional description to RTL.
Multi-level logic minimization
Typical practical implementations of a logic function utilize a multi-level network of logic elements. Starting from an RTL description of a design, the synthesis tool constructs a corresponding multilevel Boolean network.
Next, this network is optimized using several technology-independent techniques before technology-dependent optimizations are performed. Finally, technology-dependent optimization transforms the technology-independent
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